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ADT7473
FRONT
CHASSIS
FAN
ADT7473
PWM1
TACH2
TACH1
CPU FAN
REAR
CHASSIS
FAN
PWM3
TACH3
D2+
D2 ?
THERM
PROCHOT
CPU
AMBIENT
TEMPERATURE
D1+
D1 ?
SDA
SCL
SMBALERT
GND
ICH
Figure 12. ADT7473 Configuration
Serial Bus Interface
On PCs and servers, control of the ADT7473/ADT7473 ? 1
is carried out using the SMBus. The ADT7473/ADT7473 ? 1
is connected to this bus as a slave device, under the control of
a master controller, which is usually (but not necessarily) the
ICH.
The ADT7473 has a fixed 7-bit serial bus address of
ADT7473 ? 1
ADDR SELECT
PWM3/
ADDREN
4
8
V CC
10 k W
0101110 or 0x2E. The read/write bit must be added to get the
8-bit address (01011100 or 0x5C). When the ADT7473 ? 1
is powered up with Pin 8 (PWM3/ADDREN) high, the
ADT7473 ? 1 has a default SMBus address of 0101110 or
ADDRESS = 0x2E
Figure 13. Default SMBus Address = 0x2E
0x2E. If more than one ADT7473 ? 1 is used in a system,
each ADT7473 ? 1 is placed in ADDR SELECT mode by
strapping Pin 8 low on powerup. The logic state of Pin 4
then determines the device’s SMBus address. The logic of
these pins is sampled on powerup.
ADT7473 ? 1
ADDR SELECT
PWM3/
ADDREN
4
8
10 k W
The device address is sampled on powerup and latched on
the first valid SMBus transaction, more precisely on the
low-to-high transition at the beginning of the eighth SCL
pulse, when the serial bus address byte matches the selected
ADDRESS = 0x2C
Figure 14. SMBus Address = 0x2C (Pin 4 = 0)
slave address. T he selected slav e address is chosen using the
ADDREN pin/ADDR SELECT pin. Any attempted change
in the address has no effect after this.
Table 7. HARDWIRING THE ADT7473 ? 1 SMBUS
DEVICE ADDRESS
ADT7473 ? 1
ADDR SELECT
PWM3/
V CC
4
8
10 k W
Pin 13 State
0
0
1
Pin 14 State
Low (10 k W to GND)
High (10 k W Pullup)
Don’t Care
Address
0101100 (0x2C)
0101101 (0x2D)
0101110 (0x2E)
ADDR_EN
ADDRESS = 0x2D
Figure 15. SMBus Address = 0x2D (Pin 4 = 1)
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